Intel Cyclone 10 GX User Manual

Parameter Range
Enable rx_is_lockedtodata port On / Off
Enable rx_is_lockedtoref port On / Off
Enable rx_set_locktodata and rx_set_locktoref ports On / Off
Enable rx_serialpbken port On / Off
Enable PRBS verifier control and status ports On / Off
Table 144. Enhanced PCS Parameters
Parameter Range
Enhanced PCS/PMA interface width 32, 40, 64
FPGA fabric/Enhanced PCS interface width 32, 40, 50, 64, 66, 67
Enable Enhanced PCS low latency mode On / Off
Enable RX/TX FIFO double width mode On / Off
TX FIFO mode Phase compensation, Register, Interlaken, Basic, Fast
register
Note: Only Basic Enhanced is valid.
TX FIFO partially full threshold 10, 11, 12, 13, 14, 15
TX FIFO partially empty threshold 1, 2, 3, 4, 5
Enable tx_enh_fifo_full port On / Off
Enable tx_enh_fifo_pfull port On / Off
Enable tx_enh_fifo_empty port On / Off
Enable tx_enh_fifo_pempty port On / Off
RX FIFO mode Phase Compensation, Register, Basic
RX FIFO partially full threshold 0 to 31
RX FIFO partially empty threshold 0 to 31
Enable RX FIFO alignment word deletion (Interlaken) On / Off
Enable RX FIFO control word deletion (Interlaken) On / Off
Enable rx_enh_data_valid port On / Off
Enable rx_enh_fifo_full port On / Off
Enable rx_enh_fifo_pfull port On / Off
Enable rx_enh_fifo_empty port On / Off
Enable rx_enh_fifo_pempty port On / Off
Enable rx_enh_fifo_del port (10GBASE-R) On / Off
Enable rx_enh_fifo_insert port (10GBASE-R) On / Off
Enable rx_enh_fifo_rd_en port On / Off
Enable rx_enh_fifo_align_val port (Interlaken) On / Off
Enable rx_enh_fifo_align_cir port (Interlaken) On / Off
Enable TX 64b/66b encoder On / Off
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English