Intel Cyclone 10 GX User Manual

Parameter Range
Enable RX 64b/66b decoder On / Off
Enable TX sync header error insertion On / Off
Enable RX block synchronizer On / Off
Enable rx_enh_blk_lock port On / Off
Enable TX data bitslip On / Off
Enable TX data polarity inversion On / Off
Enable RX data bitslip On / Off
Enable RX data polarity inversion On / Off
Enable tx_enh_bitslip port On / Off
Enable rx_bitslip port On / Off
Enable tx_enh_frame port On / Off
Enable rx_enh_frame port On / Off
Enable rx_enh_frame_dian_status port On / Off
Table 145. Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration On / Off
Share reconfiguration interface On / Off
Enable Altera Debug Master Endpoint On / Off
Enable embedded debug On / Off
Enable capability registers On / Off
Set user-defined IP identifier number
Enable control and status registers On / Off
Enable prbs soft accumulators On / Off
Configuration file prefix text string
Generate SystemVerilog package file On / Off
Generate C header file On / Off
Table 146. Generate Options Parameters
Parameter Range
Generate parameter documentation file On / Off
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English