5.1.2.1.2. Programmable Differential On-Chip Termination (OCT)
Receiver buffers include programmable on-chip differential termination of 85Ω, 100Ω,
or OFF.
You can disable OCT and use external termination. If you select external termination,
the receiver common mode is tri-stated. Common mode is based on the external
termination connection. You will also need to implement off-chip biasing circuitry to
establish the V
CM
at the receiver buffer.
5.1.2.1.3. Signal Detector
You can enable the optional signal threshold detection circuitry. If enabled, this option
senses whether the signal level present at the receiver input buffer is above the signal
detect threshold voltage that you specified in the assignment editor.
5.1.2.1.4. Continuous Time Linear Equalization (CTLE)
The CTLE boosts the signal that is attenuated due to channel characteristics. Each
receiver buffer has independently programmable equalization circuits. These
equalization circuits amplify the high-frequency component of the incoming signal by
compensating for the low-pass characteristics of the physical medium. The CTLE can
support both DC and AC gain.
DC gain circuitry provides an equal amplification to the incoming signal across the
frequency spectrum. AC gain circuitry provides amplification to the high-frequency
spectrum gain of the incoming signal. Refer to Figure 173 on page 278.
Cyclone 10 GX transceivers support high gain mode CTLE.
High Gain Mode
This mode provides both AC and DC gain. There are two bandwidth settings available
for this mode.
• Full Bandwidth—This mode has a peaking frequency of 6.25 GHz offering AC gain
around 15 dB.
• Medium Bandwidth—This mode has a peaking frequency of 3.125 GHz offering AC
gain around 20 dB.
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
277
To Next Page
Loading...
Need help?
General
