Intel Cyclone 10 GX User Manual

a. Perform dynamic reconfiguration.
b.
Deassert pll_powerdown after t
pll_powerdown
.
c.
Deassert tx_analogreset. This step can be done at the same time or after
you deassert pll_powerdown.
3.
Wait for tx_analogreset_ack to go low, to ensure successful deassertion of
tx_analogreset. tx_analogreset_ack goes low when TRS has successfully
completed the reset request for deassertion.
4.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for
tx_analogreset_ack to go low before monitoring the pll_locked signal.
5.
Deassert tx_digitalreset a minimum t
tx_digitalreset
time after pll_locked
goes high.
Figure 159. Dynamic Reconfiguration of Transmitter Channel During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
pll_powerdown
pll_locked
tx_analogreset_ack
1 2 3 54
tx_digitalreset
t
tx_digitalreset
Legal
Reconfiguration
Window
Area in gray is don’t care zone.
Note:
(1)
4.3.2.1.4. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
The numbers in this list correspond to the numbers in the following figure.
1.
Assert rx_analogreset and rx_digitalreset while rx_cal_busy is low.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English