Intel Cyclone 10 GX User Manual

•
In this case, the PLL IP core has tx_bonding_clocks output bus with width
[5:0].
•
The Native PHY IP core has tx_bonding_clocks input bus with width [5:0]
multiplied by the number of transceiver channels (10 in this case). For 10
channels, the bus width will be [59:0].
Note:
While connecting tx_bonding_clocks, leave pll_ref_clk open to
avoid any Quartus Prime software fitter errors.
• Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for
the input port connection is .tx_bonding_clocks
({10{tx_bonding_clocks_output}}) .
Note: Although the above diagram looks similar to the 10-channel non-bonded configuration
example, the clock input ports on the transceiver channels bypass the local CGB in
x6/xN bonding configuration. This internal connection is taken care of when the
Native PHY channel bonding mode is set to Bonded.
Figure 143. x6/xN Bonding Mode —Internal Channel Connections
CDR
CGB
Ch 0
CDR
CGB
Ch 1
CDR
CGB
Ch 2
(1)
Note: (1) The local CGB is bypassed by the clock input ports in bonded mode.
(1)
(1)
Related Information
xN Clock Lines on page 214
Information on xN Clock Network Span.
3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
In this bonding mode, the channel span limitations of xN bonding mode are removed.
This is achieved by dividing all channels into multiple bonding groups.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English