Intel Cyclone 10 GX User Manual

Table 7. TX PLL Options
Parameter Value Description
TX local clock division
factor
1, 2, 4, 8 Specifies the value of the divider available in the transceiver
channels to divide the TX PLL output clock to generate the correct
frequencies for the parallel and serial clocks.
Number of TX PLL
clock inputs per
channel
1, 2, 3 , 4 Specifies the number of TX PLL clock inputs per channel. Use this
parameter when you plan to dynamically switch between TX PLL
clock sources. Up to four input sources are possible.
Initial TX PLL clock
input selection
0 to <number of TX
PLL clock inputs> -1
Specifies the initially selected TX PLL clock input. This parameter
is necessary when you plan to switch between multiple TX PLL
clock inputs.
Table 8. TX PMA Optional Ports
Parameter Value Description
Enable
tx_pma_analog_reset_ack
port
On/Off
Enables the optional tx_pma_analog_reset_ack output port.
This port should not be used for register mode data transfers.
Enable tx_pma_clkout port On/Off
Enables the optional tx_pma_clkout output clock. This is the low
speed parallel clock from the TX PMA. The source of this clock is
the serializer. It is driven by the PCS/PMA interface block.
(10)
Enable tx_pma_div_clkout
port
On/Off
Enables the optional tx_pma_div_clkout output clock. This
clock is generated by the serializer. You can use this to drive core
logic, to drive the FPGA - transceivers interface.
If you select a tx_pma_div_clkout division factor of 1 or 2,
this clock output is derived from the PMA parallel clock. If you
select a tx_pma_div_clkout division factor of 33, 40, or 66,
this clock is derived from the PMA high serial clock. This clock is
commonly used when the interface to the TX FIFO runs at a
different rate than the PMA parallel clock frequency, such as 66:40
applications.
tx_pma_div_clkout division
factor
Disabled, 1, 2,
33, 40, 66
Selects the division factor for the tx_pma_div_clkout output
clock when enabled.
(11)
Enable
tx_pma_iqtxrx_clkout port
On/Off
Enables the optional tx_pma_iqtxrx_clkout output clock. This
clock can be used to cascade the TX PMA output clock to the input
of a PLL.
Enable tx_pma_elecidle
port
On/Off
Enables the tx_pma_elecidle port. When you assert this port,
the transmitter is forced into an electrical idle condition. This port
has no effect when the transceiver is configured for PCI Express.
Enable rx_seriallpbken port On/Off
Enables the optional rx_seriallpbken control input port. The
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
Table 9. RX CDR Options
Parameter Value Description
Number of CDR reference
clocks
1 - 5 Specifies the number of CDR reference clocks. Up to 5 sources are
possible.
The default value is 1.
continued...
(10)
This clock should not be used to clock the FPGA - transceivers interface. This clock may be
used as a reference clock to an external clock cleaner.
(11)
The default value is Disabled.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English