Intel Cyclone 10 GX User Manual

Signal Name Direction Clock Domain Description
rx_cal_busy[<n> -1:0]
Input Asynchronous This is calibration status signal from the Transceiver
PHY IP core. When asserted, the initial calibration is
active. When deasserted, calibration has completed. It
will not be asserted if you manually re-trigger the
calibration IP. This signal gates the RX reset sequence.
The width of this signals depends on the number of RX
channels.
rx_is_lockedtodata[<n
>-1:0]
Input Synchronous to CDR
Provides the rx_is_lockedtodata status from each
RX CDR. When asserted, indicates that a particular RX
CDR is ready to receive input data. If you do not
choose separate controls for the RX channels, these
inputs are ANDed together internally to provide a
single status signal.
tx_manual[<n>-1:0]
Input Asynchronous
This optional signal places tx_digitalreset
controller under automatic or manual control. When
asserted, the associated tx_digitalreset controller
logic does not automatically respond to deassertion of
the pll_locked signal. However, the initial
tx_digitalreset sequence still requires a one-time
rising edge on pll_locked before proceeding. When
deasserted, the associated tx_digitalreset
controller automatically begins its reset sequence
whenever the selected pll_locked signal is
deasserted.
rx_manual[<n> -1:0]
Input Asynchronous
This optional signal places rx_digitalreset logic
controller under automatic or manual control. In
manual mode, the rx_digitalreset controller does
not respond to the assertion or deassertion of the
rx_is_lockedtodata signal. The
rx_digitalreset controller asserts rx_ready when
the rx_is_lockedtodata signal is asserted.
clock
Input N/A A free running system clock input to the Transceiver
PHY Reset Controller from which all internal logic is
driven. If a free running clock is not available, hold
reset until the system clock is stable.
reset
Input Asynchronous Asynchronous reset input to the Transceiver PHY Reset
Controller. When asserted, all configured reset outputs
are asserted. Holding the reset input signal asserted
holds all other reset outputs asserted. An option is
available to synchronize with the system clock. In
synchronous mode, the reset signal needs to stay
asserted for at least (2) clock cycles by default.
tx_digitalreset[<n>-1
:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Digital reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when any of the following conditions is true:
•
reset is asserted
•
pll_powerdown is asserted
•
pll_cal_busy is asserted
•
tx_cal_busy is asserted
•
PLL has not reached the initial lock (pll_locked
deasserted)
•
pll_locked is deasserted and tx_manual is
deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
tx_digitalreset.
continued...
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
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Intel
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Cyclone
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10 GX Transceiver PHY User Guide
265

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English