Intel Cyclone 10 GX User Manual

Table 136. TX PMA Parameters
Parameter Value
TX channel bonding mode Not Bonded / PMA Bonding Only / PMA
and PCS Bonding
TX local clock division factor 1
Number of TX PLL clock inputs per channel 1
Initial TX PLL clock input selection 0
Enable tx_pma_clkout port Off
Enable tx_pma_div_clkout port On
tx_pma_div_clkout division factor 2
Enable tx_pma_elecidle port Off
Enable rx_seriallpbken port Off
Table 137. RX PMA Parameters
Parameter Value
Number of CDR reference clocks 1
Selected CDR reference clock 0
Selected CDR reference clock frequency Select legal range defined by the Quartus Prime
software
PPM detector threshold 1000
CTLE adaptation mode manual
Enable rx_pma_clkout port Off
Enable rx_pma_div_clkout port On
rx_pma_div_clkout division factor 2
Enable rx_pma_clkslip port Off
Enable rx_is_lockedtodata port On
Enable rx_is_lockedtoref port On
Enable rx_set_locktodata and rx_set_locktoref ports Off
Enable rx_seriallpbken port Off
Enable PRBS verifier control and status ports Off
Table 138. Standard PCS Parameters
Parameters Value
Standard PCS / PMA interface width 20
FPGA fabric / Standard TX PCS interface width 32
FPGA fabric / Standard RX PCS interface width 32
Enable 'Standard PCS' low latency mode Off
TX FIFO mode register_fifo
RX FIFO mode register_fifo
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English