Intel Cyclone 10 GX User Manual

Parameters Value
Enable tx_std_pcfifo_full port Off
Enable tx_std_pcfifo_empty port Off
Enable rx_std_pcfifo_full port Off
Enable rx_std_pcfifo_empty port Off
TX byte serializer mode Serialize x2
RX byte deserializer mode Deserialize x2
Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control Off
Enable RX 8B/10B decoder On
RX rate match FIFO mode Disabled
RX rate match insert / delete -ve pattern (hex)
0x00000000
RX rate match insert / delete +ve pattern (hex)
0x00000000
Enable rx_std_rmfifo_full port Off
Enable rx_std_rmfifo_empty port Off
Enable TX bit slip Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable tx_std_bitslipboundarysel port Off (CPRI Auto configuration)
On (CPRI Manual configuration)
RX word aligner mode deterministic latency (CPRI Auto
configuration)
manual (FPGA fabric controlled) (CPRI
Manual configuration)
RX word aligner pattern length 10
RX word aligner pattern (hex)
0x000000000000017c
Number of word alignment patterns to achieve sync 3
(26)
Number of invalid data words to lose sync 3
(26)
Number of valid data words to decrement error count 3
(26)
Enable fast sync status reporting for deterministic latency SM On / Off
Enable rx_std_wa_patternalign port On / Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable rx_bitslip port Off (CPRI Auto configuration)
On (CPRI Manual configuration)
All options under Bit Reversal and Polarity Inversion Off
All options under PCIe Ports Off
(26)
These are unused when the transceiver PHY is in CPRI mode.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
157

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English