Intel Cyclone 10 GX User Manual

Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with
embedded streamer enabled. To perform a PMA reconfiguration such as TX PLL
switching, CGB divider switching, or reference clock switching, use the reconfiguration
flow for special cases described in Steps to Perform Dynamic Reconfiguration.
Table 177. Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in Native PHY IP
Reconfigur
ation
Address
(hex)
Reconfigur
ation Bit
Attribute
Name
Attribute
Description
Bit
Encoding
Transceiver Block Description
340 7 cfg_load Start
streaming
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to initiate
streaming, self-clearing bit
6 bcast_en Broadcast
enable
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to broadcast
the same profile to all the
channels
[2:0] cfg_sel Configuration
profile select
Direct
mapped
Embedded
Reconfiguration
Streamer
Binary encoding of the
configuration Profile to
stream
341 0 rcfg_busy Busy Status
bit
1'b1 Embedded
Reconfiguration
Streamer
Bit is set to:
• 1'b1—streaming is in
progress
• 1'b0—streaming is
complete
You can write to the address 0x340 at the same time to start the streaming, enable
broadcasting, and select the profile to be streamed. Different requests to multiple
channels can be made simultaneously by writing to the addresses of the desired
channels through the user reconfiguration interface (shared or independent). The
reconfig_waitrequest signal will remain asserted after the reconfiguration
streaming is complete.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 328
• Analog Parameter Settings on page 388
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English