Intel Cyclone 10 GX User Manual

Figure 207. Reconfiguration Interface in Cyclone 10 GX Transceiver IP Cores
Embedded Controller in FPGA
or Embedded Processor on PCB
Avalon-MM Master
Ch0: Avalon
Reconfiguration
Interface
Ch1: Avalon
Reconfiguration
Interface
Native PHY IP Core
Avalon
Reconfiguration
Interface
Transceiver PLL IP Core
A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL
instances, a Native PHY IP core instance can specify multiple channels. You can use a
dedicated reconfiguration interface for each channel or share a single reconfiguration
interface across all channels to perform dynamic reconfiguration.
Avalon-MM masters interact with the reconfiguration interface by performing Avalon
read and write operations to initiate dynamic reconfiguration of specific transceiver
parameters. All read and write operations must comply with Avalon-MM specifications.
Figure 208. Top-Level Signals of the Reconfiguration Interface
Native PHY IP core
or
Transceiver PLL IP core
reconfig_clk
reconfig_reset
reconfig_read
reconfig_write
reconfig_address
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
The user-accessible Avalon-MM reconfiguration interface and PreSICE Avalon-MM
interface share a single internal configuration bus. This bus is arbitrated to get access
to the Avalon-MM interface of the channel or PLL. Refer to the Arbitration section for
more details about requesting access to and returning control of the internal
configuration bus from PreSICE.
Related Information
• Arbitration on page 325
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English