EasyManuals Logo

Intel Cyclone 10 GX User Manual

Intel Cyclone 10 GX
402 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #126 background imageLoading...
Page #126 background image
For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP
ordered set where insertion or deletion occurs.
For FULL/EMPTY cases: The flag status appears where the character is inserted or
deleted.
Note: When the PIPE interface is on, it translates the value of the flag to the
appropriate pipe_rx_status[2:0] signal.
The PIPE mode also has a “0 ppm” configuration option that you can use in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency will be minimized.
Figure 58. Rate Match Deletion
This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be
deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.
K28.5 K28.0 Dx.y K28.5 K28.0 K28.0 K28.0rmfifo_input_data
First SKP Ordered Set Second SKP Ordered Set
SKP Symbol
Deleted
K28.5 Dx.y K28.5 K28.0 K28.0rx_parallel_data
pipe_rx_status[2:0]
3’b010 xxx 3’b010 xxx xxx
Dx.y
Dx.y
xxx
Figure 59. Rate Match Insertion
The figure below shows an example of rate match insertion in the case where two SKP symbols must be
inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
rmfifo_input_data
rx_parallel_data
First SKP Ordered Set
Second SKP Ordered Set
SKP Symbol Inserted
K28.5 K28.0 Dx.y K28.5 K28.0 K28.0 K28.0 K28.0
K28.5 K28.0 K28.0 Dx.y K28.5 K28.0
K28.0 K28.0 K28.0 K28.0
pipe_rx_status[2:0]
3’b001 xxx xxx xxx 3’b001 xxx
xxx xxx xxx xxx
Figure 60. Rate Match FIFO Full
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and
drives pipe_rx_status[2:0] = 3'b101 synchronous to the subsequent data byte. The figure below shows
the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte
D4.
D1 D2 D3 D4 D5 D6 D7 D8
D1 D2 D3 D4 D8 xx xx xxD6
D7
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0] xxx xxx xxx xxx 3’b101 xxx xxx xxx
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
Send Feedback
126

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel Cyclone 10 GX and is the answer not in the manual?

Intel Cyclone 10 GX Specifications

General IconGeneral
BrandIntel
ModelCyclone 10 GX
CategoryTransceiver
LanguageEnglish

Related product manuals