Intel Cyclone 10 GX

Document
Version
Changes
• Added step 5 "If you reconfigure PLL for data rate change you must recalibrate the PLL" in
Embedded Reconfiguration Streamer block of ATX PLL.
• Added "The CLKUSR pin must be assigned a 100-125 MHz clock. For used transceiver TX and RX
channels, do not assert the analog reset signals indefinitely" in "Unused/Idle Clock Line
Requirements" section.
• Added a sentence in fPLL/CMU PLL "For protocol jitter compliance at datarate > 10 Gbps, Intel
recommends using the dedicated reference clock pin in the same triplet with the fPLL/CMU PLL as
the input reference clock source."
2017.05.08 Initial release.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
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