Intel Cyclone 10 GX User Manual

Figure 11. Native PHY IP Core Ports and Functional Blocks
Reconfiguration
Registers
Enhanced PCS
Transmit and Receive Clocks
Standard PCS
Transmit
PMA
Receive
PMA
Reset Signals
Transmit Parallel Data
Reconfiguration Interface
Transmit Serial Data
Receive Serial Data
Receive Parallel Data
PCS-Direct
Nios II
Calibration
Calibration Signals
Figure 12. Native PHY IP Core Parameter Editor
Note: Although the Quartus Prime software provides legality checks, refer to the High-Speed
Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices
section of theIntel Cyclone 10 GX Device Datasheet for the supported FPGA fabric to
PCS interface widths and frequency.
Related Information
• Configure the PHY IP Core on page 19
• Interlaken on page 70
• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 87
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
27

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English