Intel Cyclone 10 GX User Manual

Parameter Range
Enable TX 8B/10B disparity control On/Off
Enable RX 8B/10B decoder On/Off
RX rate match FIFO mode
Disabled
Basic 10-bit PMA (for Basic with Rate Match)
Basic 20-bit PMA (for Basic with Rate Match)
RX rate match insert/delete -ve pattern (hex) User-defined value
RX rate match insert/delete +ve pattern (hex) User-defined value
Enable rx_std_rmfifo_full port On/Off
Enable rx_std_rmfifo_empty port On/Off
Enable TX bit slip On/Off
Enable tx_std_bitslipboundarysel port On/Off
RX word aligner mode
bitslip
manual (PLD controlled)
synchronous state machine
RX word aligner pattern length 7, 8, 10, 16, 20, 32, 40
RX word aligner pattern (hex) User-defined value
Number of word alignment patterns to achieve sync 0-255
Number of invalid data words to lose sync 0-63
Number of valid data words to decrement error count 0-255
Enable fast sync status reporting for deterministic latency SM On/Off
Enable rx_std_wa_patternalign port On/Off
Enable rx_std_wa_a1a2size port On/Off
Enable rx_std_bitslipboundarysel port On/Off
Enable rx_bitslip port On/Off
Enable TX bit reversal On/Off
Enable TX byte reversal On/Off
Enable TX polarity inversion On/Off
Enable tx_polinv port On/Off
Enable RX bit reversal On/Off
Enable rx_std_bitrev_ena port On/Off
Enable RX byte reversal On/Off
Enable rx_std_byterev_ena port On/Off
Enable RX polarity inversion On/Off
Enable rx_polinv port On/Off
Enable rx_std_signaldetect port On/Off
Enable PCIe dynamic datarate switch ports Off
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English