Deletable Case Word Previous Current Output
LW X OS X X
Upper Word 1 UW X I X X
LW X !T X !T
2 UW X OS X X
LW X OS X OS
If only one word is deleted, data shifting is necessary because the datapath is two
words wide. After two words have been deleted, the FIFO stops writing for one cycle
and a synchronous flag (rx_control[8]) appears on the next block of 8-byte data.
There is also an asynchronous status signal rx_enh_fifo_del, which does not go
through the FIFO.
Figure 192. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
00000000000004ADh 00000000000004AEh
0707070707FD0000h 000000FB07070707h
00000000000004ADh 00000000000004AEh
0707070707FD0000h
AAAAAAAA000000FBh
Idle Deleted
Before Deletion
After Deletion
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 193. OS Word Deletion
This figure shows the deletion of Ordered set words in the receiver data stream.
OS Deleted
Before Deletion
After Deletion
FD000000000004AEh 000000FBDDDDDD9Ch AAAAAAAA00000000h 00000000AAAAAAAAh
FD000000000004AEh DDDDDD9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Idle Insertion
Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty flag is
deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of
8 bytes. Data shifting is not necessary. There is a synchronous status
rx_enh_fifo_insert signal that is attached to the 8-byte Idles being inserted.
Table 170. Cases Where Two Idle Words are Inserted
In this table X=don’t care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3
and 4, the Idles are inserted between the LW and UW.
Case
Word Input Output
1 UW I-DS I-DS I-In
LW X X I-In
2 UW OS OS I-In
LW X X I-In
3 UW S I-In S
continued...
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
Intel
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Cyclone
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10 GX Transceiver PHY User Guide
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