Intel Cyclone 10 GX User Manual

Figure 27. Signals and Ports of Native PHY IP for Interlaken
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_clkout
tx_coreclkin
tx_control[17:0] (1)
tx_parallel_data[127:0] (1)
tx_enh_data_valid
tx_enh_frame_burst_en
tx_enh_frame_diag_status[1:0]
tx_enh_frame
tx_enh_fifo_cnt[3:0]
tx_enh_fifo_full
tx_enh_fifo_pfull
tx_enh_fifo_empty
tx_enh_fifo_pempty
Reconfiguration
Registers
TX Enhanced PCS
rx_clkout
rx_coreclkin
rx_parallel_data[127:0] (2)
rx_control[19:0] (2)
rx_enh_fifo_rd_en
rx_enh_data_valid
rx_enh_fifo_align_val
rx_enh_fifo_align_clr
rx_enh_frame
rx_enh_fifo_cnt[3:0]
rx_enh_fifo_full
rx_enh_fifo_pfull
rx_enh_fifo_empty
rx_enh_fifo_pempty
rx_enh_frame_diag_status[1:0]
rx_enh_frame_lock
rx_enh_crc32_err
rx_enh_blk_lock
RX Enhanced PCS
Hard
Calibration Block
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
tx_serial_data
rx_serialloopback
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
tx_serial_clk or
tx_bonding_clocks[5:0]
(from TX PLL)
Notes:
(1) The width of tx_parallel_data and tx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
tx_parallel_data = 64 bits and tx_control = 3 bits. The width shown here is without simplified interface.
(2) The width of rx_parallel_data and rx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
rx_parallel_data = 64 bits and rx_control = 10 bits. The width shown here is without simplified interface.
tx_analog_reset
rx_analog_reset
rx_digital_reset
Cyclone 10 Transceiver Native PHY
32/40/64
32/40/64
5. Configure and instantiate your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state
machine using fabric logic resources for multi-lane Interlaken implementation.
8. Connect the Native PHY IP to the PLL IP and the reset controller.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English