Intel Cyclone 10 GX User Manual

Figure 28. Connection Guidelines for an Interlaken PHY Design
This figure shows and example connection for an Interlake PHY design.
For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic and RX deskew
logic. The white blocks are your test logic or MAC layer logic.
Reset
Controller
PLL IP
Pattern
Generator
Pattern
Verifier
TX Soft
Bonding
RX
Deskew
Cyclone 10
Transceiver
Native PHY
PLL and CGB Reset
TX/RX Analog/Digital Reset
TX FIFO Status
TX Data Stream
RX Data Stream
TX FIFO Control
Control and Status
Control and Status
RX FIFO Status
RX FIFO Control
TX Clocks
9. Simulate your design to verify its functionality.
Figure 29. 12 Lanes Bonded Interlaken Link, TX Direction
To show more details, three different time segments are shown with the same zoom level.
12`h000
12`h... 12`hFFF
12`h000
12`hFFF12`h000
12`h000
12`h00012`hFFF
12`hFFF
12`hFFF 12`h000
12`h000
768'h<192_data_char>
36'h<9_kl_char>
12`h000
12`hFFF
12`...
12`h000
12`hFFF
12`hFFF
12`h000
12`h000...
12`h000
12`h000
12`h000
768'h<192_data_char>
36'h<9_kl_char>
12`h000
12`h000
12`hFFF
12`hFFF
12`hFFF
768'h<192_data_char>
36'h<9_kl_char>
12`h000
12`h000
12`hFFF
12`h000
12`h000
12`h000
12`h000
768`h...
pll_locked
tx_analogreset
tx_clkout[0]
tx_clkout
tx_digitalreset
tx_ready[0]
tx_ready
tx_enh_data_valid[0]
tx_enh_data_valid
tx_enh_fifo_full
tx_enh_frame[0]
tx_enh_frame
tx_enh_frame_burst_en[0]
tx_enh_frame_burst_en
tx_parallel_data
tx_control
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_ready
Asserted
Pre-Fill
Stage
Pre-Fill Completed
Assert burst_en for
All Lanes
Send Data
Based on
FIFO Flags
12`h000
12`h000
12`h000
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English