Intel Cyclone 10 GX User Manual

Name Range Description
value of 0 adds no hysteresis. A higher value filters
glitches on the pll_locked signal. Intel
recommends that the amount of hysteresis be
longer than tpll_lock_max_time.
RX Channel
Enable RX channel reset control On /Off When On, each RX channel has a separate reset
input. When Off, each RX channel uses a shared
RX reset input for all channels. This implies that if
one of the RX channels is not locked, all the other
RX channels will be held in reset until all RX
channels are locked. Digital reset stays asserted
until all RX channels have acquired lock.
Use separate RX reset per channel On /Off When On, each RX channel has a separate reset
input. When Off, uses a shared RX reset controller
for all channels.
RX digital reset mode Auto, Manual, Expose
Port
Specifies the Transceiver PHY Reset Controller
behavior when the PLL lock signal is deasserted.
The following modes are available:
•
Auto—The associated rx_digitalreset
controller automatically resets whenever the
rx_is_lockedtodata signal is deasserted.
•
Manual—The associated rx_digitalreset
controller is not reset when the
rx_is_lockedtodata signal is deasserted,
allowing you to choose corrective action.
•
Expose Port—The rx_manual signal is a top-
level signal of the IP core. If the core includes
separate reset control for each RX channel,
each RX channel uses its respective
rx_is_lockedtodata signal for automatic
reset control; otherwise, the inputs are ANDed
to provide internal status for the shared reset
controller.
rx_analogreset duration
1-999999999
Specifies the time in ns to continue to assert the
rx_analogreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle. The default
value is 40 ns.
Note: Model 1 requires this to be set to 70 µs.
Select the Cyclone 10 GX Default
Settings preset.
rx_digitalreset duration
1-999999999
Specifies the time in ns to continue to assert the
rx_digitalreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle. The default
value is 4000 ns.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
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Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
263

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English