Intel Cyclone 10 GX User Manual

RX bitslip is engaged when the RX block synchronizer or rx_bitslip is enabled to
shift the word boundary. On the rising edge of the bitslip signal of the RX block
synchronizer or rx_bitslip from the FPGA fabric, the word boundary is shifted by
one serial bit or 1UI. Each bit slip removes the earliest received bit from the received
data.
Figure 188. RX Bitslip
rx_bitslip is toggled two times, which shifts the rx_parallel_data boundary two bits.
00000001
00000000 00100000 00200000 00400000
tx_parallel_data (hex)
rx_parallel_data (hex)
tx_ready
rx_ready
rx_clkout
rx_bitslip
The second rising edge of rx_bitslip
makes another serial bit slip.
The first rising edge of
rx_bitslip makes 1 serial bit
The receiver gearbox can invert the polarity of the incoming data. This is useful if the
receiver signals are reversed on the board or backplane layout. Enable polarity
inversion through the Native PHY IP Parameter Editor.
Data valid generation logic is essential for gearbox operation. Each block of data is
accompanied by rx_enh_data_valid data valid signal which “qualifies” the block as
valid or not. The data valid toggling pattern is dependent on the data width conversion
ratio. For example, if the ratio is 66:40, the data valid signal is high in 20 out of 33
cycles or approximately 2 out of 3 cycles and the pattern repeats every 33
rx_clkout RX low-speed parallel clock cycles.
5.2.2.2. Block Synchronizer
The block synchronizer determines the block boundary of a 66-bit word in the case of
the 10GBASE-R protocol or a 67-bit word in the case of the Interlaken protocol. The
incoming data stream is slipped one bit at a time until a valid synchronization header
(bits 65 and 66) is detected in the received data stream. After the predefined number
of synchronization headers (as required by the protocol specification) is detected, the
block synchronizer asserts rx_enh_blk_lock (block lock status signal) to other
receiver PCS blocks down the receiver datapath and to the FPGA fabric.
Note: The block synchronizer is designed in accordance with Interlaken Protocol specification
(as described in Figure 13 of Interlaken Protocol Definition v1.2) and 10GBASE-R
protocol specification (as described in IEEE 802.3-2008 clause-49).
5.2.2.3. Interlaken Disparity Checker
The Interlaken disparity checker examines the received inversion bit inserted by the
far end disparity generator, to determine whether to reverse the inversion process of
the Interlaken disparity generation.
Note:
The Interlaken disparity checker is available to implement the Interlaken protocol.
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English