Intel Cyclone 10 GX User Manual

Port Name Direction Clock Domain Description
reconfig_writedata[31:0]
Input
reconfig_clk
A 32-bit data write bus. Data to be written
into the address indicated by
reconfig_address.
reconfig_readdata[31:0]
Output
reconfig_clk
A 32-bit data read bus. Valid data is placed on
this bus after a read operation. Signal is valid
after reconfig_waitrequest goes high and
then low.
reconfig_waitrequest
Output
reconfig_clk
A one-bit signal that indicates the Avalon
interface is busy. Keep the Avalon command
asserted until the interface is ready to proceed
with the read/write transfer. The behavior of
this signal depends on whether the feature
Separate reconfig_waitrequest from the
status of AVMM arbitration with PreSICE
is enabled or not. For more details, refer to
the Arbitration section.
When Share reconfiguration interface is off, the Native PHY IP core provides an
independent reconfiguration interface for each channel. For example, when a
reconfiguration interface is not shared for a four-channel Native PHY IP instance,
reconfig_address[9:0] corresponds to the reconfiguration address bus of logical
channel 0, reconfig_address[19:10] correspond to the reconfiguration address
bus of logical channel 1, reconfig_address[29:20] corresponds to the
reconfiguration address bus of logical channel 2, and reconfig_address[39:30]
correspond to the reconfiguration address bus of logical channel 3.
Table 192. Reconfiguration Interface Ports with Independent Native PHY
Reconfiguration Interfaces
The reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the
number of channels.
Port Name
Direction Clock Domain Description
reconfig_clk[N-1:0]
Input N/A Avalon clock for each channel. The clock
frequency is 100-125 MHz.
reconfig_reset[N-1:0]
Input
reconfig_clk
Resets the Avalon interface for each channel.
Asynchronous to assertion and synchronous to
deassertion.
reconfig_write[N-1:0]
Input
reconfig_clk
Write enable signal for each channel. Signal is
active high.
reconfig_read[N-1:0]
Input
reconfig_clk
Read enable signal for each channel. Signal is
active high.
reconfig_address[N*10-1:0]
Input
reconfig_clk
A 10-bit address bus for each channel.
reconfig_writedata[N*32-1:0]
Input
reconfig_clk
A 32-bit data write bus for each channel. Data
to be written into the address indicated by the
corresponding address field in
reconfig_address.
reconfig_readdata[N*32-1:0]
Output
reconfig_clk
A 32-bit data read bus for each channel. Valid
data is placed on this bus after a read
operation. Signal is valid after waitrequest
goes high and then low.
reconfig_waitrequest[N-1:0]
Output
reconfig_clk
A one-bit signal for each channel that
indicates the Avalon interface is busy. Keep
the Avalon command asserted until the
interface is ready to proceed with the read/
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English