Intel Cyclone 10 GX User Manual

There are two ways to check who has the access to the internal configuration bus:
•
Use reconfig_waitrequest
• Use capability registers
The Native PHY IP core and PLL default setting is to use reconfig_waitrequest.
When PreSICE controls the internal configuration bus, the reconfig_waitrequest
from the internal configuration bus is high. When user access is granted, the
reconfig_waitrequest from the internal configuration bus goes low. At the Avalon-
MM reconfiguration interface, the reconfig_waitrequest can come from a few
places inside Native PHY IP core. For example, it can come from the internal
configuration bus, streamer, and so on. They are bundled together and become single
reconfig_waitrequest at the Avalon-MM reconfiguration interface. The
reconfig_address determines which reconfig_waitrequest to show at the
Avalon-MM reconfiguration interface. After you return the internal configuration bus to
PreSICE, the reconfig_waitrequest from the internal configuration bus is high. If
you set the reconfig_address to the streamer offset address at the Avalon-MM
reconfiguration interface during calibration, the reconfig_waitrequest can be low
before calibration is finished. If you keep the reconfig_address the same as the
internal configuration bus offset address during calibration, the
reconfig_waitrequest at the Avalon-MM reconfiguration interface will be high until
PreSICE returns the internal configuration bus to you. It is important to keep
reconfig_address static during calibration.
To use capability registers to check bus arbitration, you can do the following when
generating the IP:
1. Select Enable dynamic reconfiguration from the Dynamic Reconfiguration
tab.
2. Select both the Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers options.
You can read the capability register 0x281[2] to check who is controlling the channel
access, and read the capability register 0x280[2] to check who is controlling the PLL
access. When Separate reconfig_waitrequest from the status of AVMM
arbitration with PreSICE and Enable control and status registers are enabled,
the reconfig_waitrequest will not be asserted high when PreSICE controls the
internal configuration bus.
To return the internal configuration bus to PreSICE:
• Write 0x1 to offset address 0x0[7:0] if any calibration bit is enabled from
offset address 0x100.
• Write 0x3 to offset address 0x0[7:0] if no calibration bit has been
enabled from offset address 0x100.
To check if the calibration process is running, do one of the following:
•
Monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busy signals.
•
Read the *_cal_busy signal status from the capability registers.
The *_cal_busy signals remain asserted as long as the calibration process is
running. To check whether or not calibration is done, you can read the capability
registers or check the *_cal_busy signals. The reconfig_waitrequest from the
Avalon-MM reconfiguration interface is not a reliable indicator to check whether or not
7. Calibration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English