Intel Cyclone 10 GX User Manual

7.2.5.1. Rules to Build Customized Gating Logic to Separate tx_cal_busy and
rx_cal_busy signals
Figure 221. An Example of an AND Gate used as Customized Logic
The customized gates shown in the following figure are an example and not a unique solution
Simplex
TX
reset
Simplex
RX
reset
Reset
Contoller
tx_cal_busy
rx_cal_busy
tx/rx_cal_busy_out
tx_cal_busy_out_en
rx_cal_busy_out_en
Customized Gates
Reset
Controller
JTAG to
Avalon
Master
Bridge
reset
reset
The capability register is not available when merging a Simplex TX and a Simplex RX
signal into the same physical channel. The tx_cal_busy_out and
rx_cal_busy_out signals share the same port. So, you should build customized
gating logic to separate them.
•
The tx_cal_busy_out_en signal enables the tx_cal_busy output.
•
The rx_cal_busy_out_en signal enables the rx_cal_busy output.
•
At power up, tx_cal_busy_out_en and rx_cal_busy_out_en should be set to
“1”.
• At normal operation:
—
When the RX is calibrating, setting tx_cal_busy_out_en to “0” and
rx_cal_busy_out_en to “1” disables tx_cal_busy, so the TX does not reset
while RX is calibrating.
—
When the TX is calibrating, setting rx_cal_busy_out_en to “0” and
tx_cal_busy_out_en to “1” disables rx_cal_busy, so the RX does not
reset while TX is calibrating.
7.2.5.2. PMA Capability Registers for Calibration Status
Bit
Description
0x281[5]
PMA channel rx_cal_busy output enable. The power up default value is 0x1.
0x1: The rx_cal_busy output and 0x281[1] are asserted high whenever PMA TX
or RX calibration is running.
0x0: The rx_cal_busy output or 0x281[1] will never be asserted high.
0x281[4]
PMA channel tx_cal_busy output enable. The power up default value is 0x1.
0x1: The tx_cal_busy output and 0x281[0] are asserted high whenever PMA TX
or RX calibration is running.
0x0: The tx_cal_busy output or 0x281[0] will never be asserted high.
0x281[2] PreSICE Avalon-MM interface control. This register is available to check who
controls the bus, no matter if, separate reconfig_waitrequest from the status
of AVMM arbitration with PreSICE is enabled or not.
0x1: PreSICE is controlling the internal configuration bus.
continued...
7. Calibration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English