Intel Cyclone 10 GX User Manual

Figure 35. rx_syncstatus High
Three Consecutive Ordered Sets Received to Achieve Synchronization
c5 bc 50 bcbc 50 8d8c 00 8c 8drx_parallel_data
rx_datak
rx_syncstatus
rx_patterndetect
rx_disperr
rx_errdetect
Related Information
Word Aligner on page 305
2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2
The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data
value and 1-bit control value as output.
Figure 36. Decoding for GbE
Dx.y(0x8d), Dx.y(0xa4), K28.5(0xbc), and Dx.y(0x50) are received at rx_parallel_data. /K28.5/ is set as
the word alignment pattern. rx_patterndetect goes high whenever it detects /K28.5/(0xbc). rx_datak is
high when bc is received, indicating that the decoded word is a control word. Otherwise, rx_datak is low.
rx_runningdisp is high for 0x8d, indicating that the decoded word has negative disparity and 0xa4 has
positive disparity.
8d
rx_datak
rx_parallel_data a4 bc 50 8d a4 bc 50 8d a4 bc 50 508d a4 bc
rx_patterndetect
rx_disperr
rx_errdetect
rx_runningdisp
Related Information
8B/10B Decoder on page 311
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English