9
9-30
DMAC
32180 Group User’s Manual (Rev.1.0)
Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5
REQSL5 DMA Transfer Request Source DMA Transfer Request Generation Timing
0 0 Software start or one DMA7 When any data is written to the DMA5 Software Request Generation Register
transfer completed (software start) or when one DMA7 transfer is completed (cascade mode)
0 1 All DMA0 transfers completed When all DMA0 transfers are completed (cascade mode)
1 0 Serial I/O2 (reception completed) When serial I/O2 reception is completed
1 1 Extended DMA5 transfer request The source selected by the DMA5 Channel Control Register 1 (DM5CNT1)
source selected REQESEL5 bits (see below)
REQESEL5 DMA Transfer Request Source DMA Transfer Request Generation Timing
0000 MJT (TIN20 input signal) When MJT TIN20 input signal is generated
0001 MJT (TOU0_0irq) MJT TOU0_0 interrupt source
0010 MJT (TOU2_7irq) MJT TOU2_7 interrupt source
0011 MJT (input event bus 1) When MJT input event bus 1 signal is generated
0100 MJT (input event bus 3) When MJT input event bus 3 signal is generated
0101 MJT (output event bus 2) When MJT output event bus 2 signal is generated
0110 MJT (output event bus 3) When MJT output event bus 3 signal is generated
0111 A-D0 conversion completed When A-D0 conversion is completed
1000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated
1001 MJT (TIO8_udf) When MJT TIO8 underflow occurs
1010
| Settings inhibited –
1111
Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6
REQSL6 DMA Transfer Request Source DMA Transfer Request Generation Timing
0 0 Software start When any data is written to the DMA4 Software Request Generation Register
0 1 Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty
1 0 MJT (TIN1 input signal) When MJT TIN1 input signal is generated
1 1 Extended DMA6 transfer request The source selected by the DMA6 Channel Control Register 1 (DM6CNT1)
source selected REQESEL6 bits (see below)
REQESEL6 DMA Transfer Request Source DMA Transfer Request Generation Timing
0000 One DMA5 transfer completed When one DMA5 transfer is completed (cascade mode)
0001 MJT (TOU0_1irq) MJT TOU0_1 interrupt source
0010 Serial I/O1 (reception completed) When serial I/O1 reception is completed
0011 MJT (input event bus 1) When MJT input event bus 1 signal is generated
0100 MJT (input event bus 3) When MJT input event bus 3 signal is generated
0101 MJT (output event bus 2) When MJT output event bus 2 signal is generated
0110 MJT (output event bus 3) When MJT output event bus 3 signal is generated
0111 A-D0 conversion completed When A-D0 conversion is completed
1000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated
1001 MJT (TIO8_udf) When MJT TIO8 underflow occurs
1010
| Settings inhibited –
1111
9.3 Functional Description of the DMAC
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