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General| Brand | Renesas |
|---|---|
| Model | M32R/ECU Series |
| Category | Computer Hardware |
| Language | English |
Explains the conventions used in register tables, including bit numbering, register borders, status after reset, shaded bits, and read/write conditions.
Provides an overview of the 32180 group, belonging to the M32R/ECU series of Mitsubishi microcomputers.
Describes the functions of each pin on the 32180, including primary and alternative functions.
Provides the pin assignment diagram and table for the 240QFP package.
Details the types of exceptions (RIE, AE, FPE), underflow, inexact, and zero division exceptions.
Shows a register map associated with the Interrupt Controller (ICU), including Interrupt Vector Register and Interrupt Request Mask Register.
Details the types of memory contained within the 32180: 48-Kbyte RAM and 1-Mbyte flash memory.
Explains the methods for programming or erasing the internal flash memory, including boot mode and single-chip mode.
Describes the microcomputer reset mechanism via the RESET# input pin and the execution from the reset vector entry.
Details reset operations such as power-on reset, reset during operation, reset at entering RAM backup mode, and reset vector relocation during flash programming.
Details the total number of input/output ports and their dual/triple function capabilities.
Explains how pin functions are selected based on the current operation mode or by setting port operation mode registers.
Lists the port data registers, port direction registers, and port operation mode registers.
Shows a memory map of the DMAC related registers, including channel control, source address, and destination address registers.
Introduces the multijunction timers (MJT), their input/output event buses, and the six types of MJT provided.
Details the common units within MJTs: Prescaler, Clock Bus, Input/Output Event Bus Control, Input Processing, Output Flip-flop, and Interrupt Control Units.
Describes the TOP timer, its specifications, modes of operation (single-shot, delayed, continuous), and interrupt generation.
Shows the A-D converter related register map, including single mode, scan mode, and data registers.
Explains how to find analog input voltages, A-D conversion by successive approximation, comparator operation, and conversion time.
Shows the serial I/O related register map, including interrupt and buffer registers.
Provides the CAN module related register map, covering control, status, frame format, and mask registers.
Explains the RTD as a serial I/O for reading/writing internal RAM locations via external commands without stopping the CPU.
Details RTD operations for commands like VER, VEI, RDR, WRR, and RCV.
Shows the register map for the external bus interface, including port operation mode registers.
Shows the Wait Controller related register map, including CS Area Wait Control Registers.
Describes RAM backup mode where internal RAM contents are retained when power is off, used for power saving or when power is down.
Lists the absolute maximum ratings for various parameters such as power supply, input/output voltage, and temperature.
Details precautions for programming/erasing internal flash memory, including voltage transitions and pin usage.
