PCS Skew InsertionPCS Skew Insertion
WAN OH CaptureWAN OH Capture
Frame CaptureFrame Capture
TransceiverTransceiver
BER testBER test
Bits:
0 to 4224 (For 100 Gbps Tx lane),
0 to 8448 (For 40 Gbps, 100 Gbps Physical lane)
Item
SOH/TOH: 64 Frames
POH: 64 Frames
Pathtrace:J0/J1/J2 (Displays in ASCII characters)
Timing
Single
Repeat : Update period 1s
Buffer size
1, 2, 4, 8, 16, 32, 64, 128 MB for 10M/100M/1000M/10G interface
512 KB for 40G/100G interface
Frame slicing
Whole frame, Top 64 Bytes, Top 32 Bytes
Buffer handling
Stop when full, Overwrite
Capture transmitted frames
on, off
Trigger Type
Manual, Error, Field match
Trigger Position
Top, Middle (Only when Trigger Type is Error/Field match)
Error Type
Any Type, Fragment, Oversize or undersize, Oversize, Undersize, FCS error
Module Present
Transceiver Information
Alarm, Wavelength and bit rate, Compliance, Vendor Information, Output
Control
Power monitor
MDIO analysis
For CFP4:
NVR1, NVR2, Module FAWS, MW Lane FAWS, CTRL, MDIO Read/Write
I2C analysis
For QSFP+ and QSFP28:
Lower, Lower (Lane), Upper (00), Upper (03), Read/Write
Setting
VOD, Pre, Post, DFE, Insertion loss
Generation and detection of test patterns. Count of errors in received test
pattern. Pattern generation:
Unframed (layer 1)
Framed with Ethernet (MAC) header (layer 2)
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