Intel Cyclone 10 GX User Manual

The protocol is applicable to systems communicating by local area networks including,
but not limited to, Ethernet. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
Figure 45. Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
(self sync) mode
Parallel Clock
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Parallel Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Register Mode
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_coreclkin
tx_clkout
10.3125 Gbps
5156.25 MHz (data rate/2) (1)
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
40
66
@ 257.8125 MHz (2)
TX XGMII
@ 156.25 MHz
RX XGMII
@ 156.25 MHz
@ 257.8125 MHz (2)
40
66
64
64
Soft Phase
Compensation
FIFO
Soft Clock
Compensation
FIFO
64 (data) + 8 (control)
Register Mode
64 (data) + 8 (control)
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R
The XGMII interface, specified by IEEE 802.3-2008, defines the 32-bit data and 4-bit
wide control character. These characters are clocked between the MAC/RS and the PCS
at both the positive and negative edge (double data rate – DDR) of the 156.25 MHz
interface clock.
The transceivers do not support the XGMII interface to the MAC/RS as defined in the
IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control
single data rate (SDR) interface between the MAC/RS and the PCS.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English