Intel Cyclone 10 GX User Manual

A PMA is the transceiver's electrical interface to the physical medium. The transceiver
PMA consists of standard blocks such as:
• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS
blocks are fed by multiple clock networks driven by high performance PLLs. In PCS
Direct configuration, the data flow is through the PCS block, but all the internal PCS
blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA
fabric.
1.2.2.1. The Transceiver Channel
Figure 6. Transceiver Channel in Full Duplex Mode
Standard PCS
Enhanced PCS
PCS Direct
Hard IP
(Optional)
Soft PIPE
(Optional)
FPGA Fabric
Transmitter PCS
Transmitter PMA
Serializer
Standard PCS
Enhanced PCS
PCS Direct
Receiver PCS
Receiver PMA
DeserializerCDR
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
(1)
(1)
(1)
(1)
Intel Cyclone 10 GX transceiver channels have three types of PCS blocks that together
support continuous data rates between 1.0 Gbps and 10.81344 Gbps.
Table 2. PCS Types Supported by Transceiver Channels
PCS Type Data Rate
Standard PCS 1.0 Gbps to 10.81344 Gbps
Enhanced PCS 1.0 Gbps to 12.5 Gbps
PCS Direct 1.0 Gbps to 12.5 Gbps
Note: The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver.
For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the
transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied
at the receiver.
1. Intel
®
Cyclone
®
10 GX Transceiver PHY Overview
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English