Intel Cyclone 10 GX User Manual

Parameter Gen1 PIPE Gen2 PIPE
RX FIFO mode
low_latency low_latency
Enable tx_std_pcfifo_full port
Optional Optional
Enable tx_std_pcfifo_empty port
Optional Optional
Enable rx_std_pcfifo_full port
Optional Optional
Enable rx_std_pcfifo_empty port
Optional Optional
Byte Serializer and Deserializer
TX byte serializer mode Disabled, Serialize x2 Serialize x2
RX byte deserializer mode Disabled, Serialize x2 Serialize x2
8B/10B Encoder and Decoder
Enable TX 8B/10B encoder Enabled Enabled
Enable TX 8B/10B disparity control Enabled Enabled
Enable RX 8B/10B decoder Enabled Enabled
Rate Match FIFO
Rate Match FIFO mode PIPE, PIPE 0ppm PIPE, PIPE 0ppm
RX rate match insert / delete -ve pattern (hex) 0x0002f17c (K28.5/K28.0/) 0x0002f17c (K28.5/K28.0/)
RX rate match insert / delete +ve pattern (hex) 0x000d0e83 (K28.5/K28.0/) 0x000d0e83 (K28.5/K28.0/)
Enable rx_std_rmfifo_full port
Optional Optional
Enable rx_std_rmfifo_empty port
Optional Optional
Word Aligner and Bit Slip
Enable TX bit slip Off Off
Enable tx_std_bitslipboundarysel port
Optional Optional
RX word aligner mode Synchronous State Machine Synchronous State Machine
RX word aligner pattern length 10 10
RX word aligner pattern (hex) 0x0000 00000000017c (/K28.5/) 0x0000 00000000017c (/K28.5/)
Number of word alignment patterns to achieve
sync
3 3
Number of invalid data words to lose sync 16 16
Number of valid data words to decrement error
count
15 15
Enable rx_std_wa_patternalign port
Optional Optional
Enable rx_std_wa_a1a2size port
Off Off
Enable rx_std_bitslipboundarysel port
Optional Optional
Enable rx_bitslip port
Off Off
Bit Reversal and Polarity Inversion
Enable TX bit reversal Off Off
Enable TX byte reversal Off Off
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English