Intel Cyclone 10 GX User Manual

Table 122. Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - RX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE
RX CDR Options
Number of CDR reference clocks 1 1
Selected CDR reference clock 0 0
Selected CDR reference clock frequency 100, 125 MHz 100, 125 MHz
PPM detector threshold 1000 1000
Equalization
CTLE adaptation mode Manual Manual
DFE adaptation mode Disabled Disabled
Number of fixed dfe taps NA NA
RX PMA Optional Ports
Enable rx_analog_reset_ack port
Optional Optional
Enable rx_pma_clkout port
Optional Optional
Enable rx_pma_div_clkout port
Optional Optional
rx_pma_div_clkout division factor
Optional Optional
Enable rx_pma_clkslip port
Optional Optional
Enable rx_is_lockedtodata port
Optional Optional
Enable rx_is_lockedtoref port
Optional Optional
Enable rx_set_locktodata and
rx_set_locktoref ports
Optional Optional
Enable rx_seriallpbken port
Optional Optional
Enable PRBS Verifier Control and Status ports Optional Optional
Table 123. Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes -
Standard PCS
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Gen1 PIPE Gen2 PIPE
Standard PCS configurations
Standard PCS / PMA interface width 10 10
FPGA Fabric / Standard TX PCS interface width 8, 16 16
FPGA Fabric / Standard RX PCS interface width 8, 16 16
Enable Standard PCS low latency mode Off Off
Standard PCS FIFO
TX FIFO mode
low_latency low_latency
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English