Intel Cyclone 10 GX User Manual

Note:
The rx_parallel_data values in the following figures are based on the TX and RX
bit reversal features being disabled.
Figure 106. TX Bit Slip in 8-bit Mode
tx_parallel_data = 8'hbc. tx_std_bitslipboundarysel = 5'b00001 (bit slip by 1 bit).
tx_std_bitslipboundarysel
tx_parallel_data
rx_parallel_data
00001
bc
79
Figure 107. TX Bit Slip in 10-bit Mode
tx_parallel_data = 10'h3bc. tx_std_bitslipboundarysel = 5'b00011 (bit slip by 3 bits).
tx_std_bitslipboundarysel
tx_parallel_data
rx_parallel_data
00011
3bc
1e7
Figure 108. TX Bit Slip in 16-bit Mode
tx_parallel_data = 16'hfcbc. tx_std_bitslipboundarysel =5'b00011 (bit slip by 3 bits).
tx_std_bitslipboundarysel
tx_parallel_data
rx_parallel_data
00011
fcbc
5e7f
Figure 109. TX Bit Slip in 20-bit Mode
tx_parallel_data = 20'hF3CBC. tx_std_bitslipboundarysel = 5'b00111 (bit slip by 7 bits).
tx_std_bitslipboundarysel
tx_parallel_data
rx_parallel_data
00111
f3cbc
e5e1f
2.9.2.13. TX Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be
swapped during board layout. Solutions such as a board respin or major updates to
the PLD logic can be expensive. The transmitter polarity inversion feature is provided
to correct this situation.
Transmitter polarity inversion can be enabled in low latency, basic, and basic rate
match modes.
To enable TX polarity inversion, select the Enable tx_polinv port option in Platform
Designer. It can also be dynamically controlled with dynamic reconfiguration.
This mode adds tx_polinv. If there is more than one channel in the design,
tx_polinv is a bus with each bit corresponding to a channel. As long as tx_polinv
is asserted, the TX data transmitted has a reverse polarity.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English