Intel Cyclone 10 GX

Figure 137. Integer Mode phase aligned and external feedback
pm_iqtxrx_t[5:0]
0 1 2 3 4 5
Ch5
4
6
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
RX pin (1)
RX pin (1)
RX pin (1)
RX pin (1)
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
ch5_iqtxrxclk_2
pm_iqtxrxclk_top[5:0]
pm_iqtxrxclk_top[3:0]
ch5_iqtxrxclk_5
Ch4
4
6
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
PMA_RX_CLK
PMA_TX_CLK
ch4_iqtxrxclk_4
pm_iqtxrxclk_top[5:0]
pm_iqtxrxclk_top[3:0]
ch4_iqtxrxclk_4
Ch3
4
6
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
PMA_RX_CLK
PMA_TX_CLK
ch3_iqtxrxclk_0
pm_iqtxrxclk_top[5:0]
pm_iqtxrxclk_top[3:0]
ch3_iqtxrxclk_5
fPLL 1
6
4
refclk
fbclk
fpll_t_iqtxrxclk
pm_iqtxrxclk_top[5:0]
pm_iqtxrxclk_top[3:0]
C
ATX PLL 1
6
4
refclk
fbclk
lc_t_iqtxrxclk
pm_iqtxrxclk_top[5:0]
pm_iqtxrxclk_top[3:0]
M
Master
CGB 1
Note: (1) RX pin used as reference clock
Related Information
• User Recalibration on page 383
• Implementing PLL Cascading on page 240
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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