Intel Cyclone 10 GX User Manual

Parameter Value Description
The default value is Off.
Enable simplified data
interface
On/Off
By default, all 128-bits are ports for the tx_parallel_data and
rx_parallel_data buses are exposed. You must understand the
mapping of data and control signals within the interface. Refer to
the Enhanced PCS TX and RX Control Ports section for details
about mapping of data and control signals.
When you turn on this option, the Native PHY IP core presents a
simplified data and control interface between the FPGA fabric and
transceiver. Only the sub-set of the 128-bits that are active for a
particular FPGA fabric width are ports.
The default value is Off.
(9)
Provide separate
interface for each
channel
On/Off When selected the Native PHY IP core presents separate data,
reset and clock interfaces for each channel rather than a wide bus.
Table 5. Transceiver Configuration Rule Parameters
Transceiver Configuration Setting Description
Basic/Custom (Standard PCS) Enforces a standard set of rules within the Standard PCS. Select these rules to
implement custom protocols requiring blocks within the Standard PCS or
protocols not covered by the other configuration rules.
Basic/Custom w /Rate Match
(Standard PCS)
Enforces a standard set of rules including rules for the Rate Match FIFO within
the Standard PCS. Select these rules to implement custom protocols requiring
blocks within the Standard PCS or protocols not covered by the other
configuration rules.
CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is
set to Auto. In Auto mode, the word aligner is set to deterministic latency.
CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner mode is
set to Manual. In Manual mode, logic in the FPGA fabric controls the word
aligner.
GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time protocol
(PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE Enforces rules for a Gen1 PCIe
®
PIPE interface that you can connect to a soft
MAC and Data Link Layer.
Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC
and Data Link Layer.
Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules to
implement protocols requiring blocks within the Enhanced PCS or protocols not
covered by the other configuration rules.
Interlaken Enforces rules required by the Interlaken protocol.
10GBASE-R Enforces rules required by the 10GBASE-R protocol.
10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled.
PCS Direct Enforces rules required by the PCS Direct mode. In this configuration the data
flows through the PCS channel, but all the internal PCS blocks are bypassed. If
required, the PCS functionality can be implemented in the FPGA fabric.
(9)
This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths,
or reconfigure the interface of the transceiver.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English