Intel Cyclone 10 GX User Manual

5.3.1.3.1. 8B/10B Encoder Control Code Encoding
Figure 199. Control Code Encoding Diagram
tx_clkout
8378 BCBC 0F00 BF3C
0 1 0
D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D28.1
tx_parallel_data[15:0]
tx_datak[1:0]
Code Group
The tx_datak signal indicates whether the 8-bit data being sent at the
tx_parallel_data port should be a control word or a data word. When tx_datak
is high, the 8-bit data is encoded as a control word (Kx.y). When tx_datak is low,
the 8-bit data is encoded as a data word (Dx.y). Depending upon the PCS-PMA
interface width, the width of tx_datak is either 1 bit or 2 bits. When the PCS-PMA
interface width is 10 bits, tx_datak is a 1-bit word. When the PCS-PMA interface
width is 20 bits, tx_datak is a 2-bit word. The LSB of tx_datak corresponds to the
LSByte of the input data sent to the 8B/10B encoder and the MSB corresponds to the
MSByte of the input data sent to the 8B/10B encoder.
Related Information
Refer to Specifications & Additional Information for more information about 8B/10B
encoder codes.
5.3.1.3.2. 8B/10B Encoder Reset Condition
The tx_digitalreset signal resets the 8B/10B encoder. During the reset condition,
the 8B/10B encoder outputs K28.5 continuously until tx_digitalreset goes low.
5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature
The idle character replacement feature is used in protocols such as Gigabit Ethernet,
which requires the running disparity to be maintained during idle sequences. During
these idle sequences, the running disparity has to be maintained such that the first
byte of the next packet always starts when the running disparity of the current packet
is negative.
When an ordered set, which consists of two code-groups, is received by the 8B/10B
encoder, the second code group will be converted into /I1/ or /I2 so that the final
running disparity of the data code-group is negative. The first code group is /K28.5/
and the second code group is a data code-group other than /D21.5/ or /D2.2/. The
ordered set /I1/ (/K28.5/D5.6/) is used to flip the running disparity and /I2/ (/K28.5/
D16.2/) is used to preserve the running disparity.
5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature
The 8B/10B encoder performs a running disparity check on the 10-bit output data.
The running disparity can also be controlled using tx_forcedisp and tx_dispval.
When the PCS-PMA interface width is 10 bits, tx_forcedisp and tx_dispval are
one bit each. When the PCS-PMA interface width is 20 bits, tx_forcedisp and
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English