Transceiver fPLL Port Description Address Bits
N/A
fPLL refclk selection MUX_0.
0x114 [7:0]
pll_refclk0 Represents logical refclk0 for MUX_1. Lookup
register x11D[4:0] stores the mapping from logical
refclk0 to the physical refclk for MUX_1.
0x11D (Lookup Register) [7:0]
pll_refclk1 Represents logical refclk1 for MUX_1. Lookup
register x11E[4:0] stores the mapping from logical
refclk1 to the physical refclk for MUX_1.
0x11E (Lookup Register) [7:0]
pll_refclk2 Represents logical refclk2 for MUX_1. Lookup
register x11F[4:0] stores the mapping from logical
refclk2 to the physical refclk for MUX_1.
0x11F (Lookup Register) [7:0]
pll_refclk3 Represents logical refclk3 for MUX_1. Lookup
register x120[4:0] stores the mapping from logical
refclk3 to the physical refclk for MUX_1.
0x120 (Lookup Register) [7:0]
pll_refclk4 Represents logical refclk4 for MUX_1. Lookup
register x121[4:0] stores the mapping from logical
refclk4 to the physical refclk for MUX_1.
0x121 (Lookup Register) [7:0]
N/A
fPLL refclk selection MUX_1.
0x11C [7:0]
Specify the logical reference clock and respective address and bits of the replacement
clock when performing a reference clock switch. Follow this procedure to switch to the
selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register for MUX 0 and save the required 5-bit pattern. For
example, switching to logical refclk3 requires use of bits[4:0] at address 0x11A.
3. Perform a read-modify-write to bits [4:0] at address 0x114 using the 5-bit value
obtained from the lookup register.
4. Read from the lookup register for MUX 1 and save the required 5-bit pattern. For
example, switching to logical refclk3 requires use of bits[4:0] at address 0x120.
5. Perform a read-modify-write to bits [4:0] at address 0x11C using the 5-bit value
obtained from the lookup register.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration on page 328
6.11.2.3. CDR and CMU Reference Clock Switching
You can use the reconfiguration interface to specify which reference clock source
drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five
different reference clock sources.
Before initiating a reference clock switch, ensure that your CDR and CMU defines more
than one reference clock source. For the CDR, specify the parameter on the RX PMA
tab during the Native PHY IP parameterization. For the CMU, specify the Number of
PLL reference clocks under the PLL tab when parameterizing the CMU PLL.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
337
To Next Page
Loading...
Need help?
General
