When performing a reference clock switch, you must specify the lookup register
address and respective bits of the replacement clock. After determining the ATX PLL,
follow this procedure to switch to the selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register address and save the required 8-bit pattern. For
example, switching to logical refclk2 requires use of bits[7:0] at address
0x115.
3.
Perform a read-modify-write to bits [7:0] at address 0x112 using the 8-bit value
obtained from the lookup register.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
Steps to Perform Dynamic Reconfiguration on page 328
6.11.2.2. fPLL Reference Clock Switching
You can use the reconfiguration interface on the fPLL instance to specify which
reference clock source drives the fPLL. The fPLL supports clocking by up to five
different reference clock sources. The flow to select between the different reference
clock sources is independent of the number of transmitter PLLs specified in the
reconfiguration interface.
Before initiating a reference clock switch, ensure that your fPLL instance defines more
than one reference clock source. Specify the Number of PLL reference clocks
parameter on the PLL tab during fPLL parameterization.
The following table shows the addresses and bits for switching between fPLL reference
clock inputs. The number of exposed pll_refclk ports varies according to the
number of reference clocks you specify. Use the fPLL reconfiguration interface for this
operation.
Table 181. Register Map for Switching fPLL Reference Clock Inputs
Transceiver fPLL Port Description Address Bits
pll_refclk0 Represents logical refclk0 for MUX_0. Lookup
register x117[4:0] stores the mapping from logical
refclk0 to the physical refclk for MUX_0.
0x117 (Lookup Register) [7:0]
pll_refclk1 Represents logical refclk1 for MUX_0. Lookup
register x118[4:0] stores the mapping from logical
refclk1 to the physical refclk for MUX_0.
0x118 (Lookup Register) [7:0]
pll_refclk2 Represents logical refclk2 for MUX_0. Lookup
register x119[4:0] stores the mapping from logical
refclk2 to the physical refclk for MUX_0.
0x119 (Lookup Register) [7:0]
pll_refclk3 Represents logical refclk3 for MUX_0. Lookup
register x11A[4:0] stores the mapping from logical
refclk3 to the physical refclk for MUX_0.
0x11A (Lookup Register) [7:0]
pll_refclk4 Represents logical refclk4 for MUX_0. Lookup
register x11B[4:0] stores the mapping from logical
refclk4 to the physical refclk for MUX_0.
0x11B (Lookup Register) [7:0]
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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