Intel Cyclone 10 GX User Manual

Parameter Value Description
Generate SystemVerilog package
file
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a SystemVerilog package file that contains the current
configuration data values for all reconfiguration addresses.
Disabled by default.
Generate C header file On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a C header file that contains the current configuration data values
for all reconfiguration addresses. Disabled by default.
Generate MIF (Memory Initialize
File)
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a MIF file that contains the current configuration data values for
all reconfiguration addresses. Disabled by default.
Include PMA analog settings in
the configuration files
On / Off Available in Native PHY IP parameter editor only. When enabled,
the IP allows you to configure the analog settings for the PMA.
These settings will be included in your generated configuration
files.
Note: Even with this option enabled in the Native PHY IP
Parameter Editor, you must still specify QSF assignments
for your analog settings when compiling your static
design. The analog settings selected in the Native PHY IP
Parameter Editor are used only to include these settings
and their dependent settings in the selected configuration
files. For details about QSF assignments for the analog
settings, refer to the Analog Parameter Settings chapter.
Enable multiple reconfiguration
profiles
On / Off Available in Native PHY and ATX PLL IP parameter editors only.
Use the Parameter Editor to store multiple configurations. The
parameter settings for each profile are tabulated in the Parameter
Editor.
Enable embedded reconfiguration
streamer
On / Off Available in Native PHY and ATX PLL IP parameter editors only.
Embeds the reconfiguration streamer into the Native PHY/ATX PLL
IP cores and automates the dynamic reconfiguration process
between multiple predefined configuration profiles.
Generate reduced
reconfiguration files
On / Off Available in Native PHY and ATX PLL IP parameter editors only.
Enables the Native PHY and ATX PLL IP cores to generate
reconfiguration files that contain only the attributes that differ
between multiple profiles.
Number of reconfiguration
profiles
1 to 8 Available in Native PHY and ATX PLL IP parameter editors only.
Specifies the number of reconfiguration profiles to support when
multiple reconfiguration profiles are enabled.
Selected reconfiguration profile 0 to 7 Available in Native PHY and ATX PLL IP parameter editors only.
Selects which reconfiguration profile to store when you click
Store profile.
Store configuration to selected
profile
N/A Available in Native PHY and ATX PLL IP parameter editors only.
Stores the current Native PHY and ATX PLL parameter settings to
the profile specified by the Selected reconfiguration profile
parameter.
Load configuration from selected
profile
N/A Available in Native PHY and ATX PLL IP parameter editors only.
Loads the current Native PHY/ATX PLL IP with parameter settings
from the stored profile specified by the Selected
reconfiguration profile parameter.
Clear selected profile N/A Available in Native PHY and ATX PLL IP parameter editors only.
Clears the stored Native PHY/ATX PLL IP parameter settings for
the profile specified by the Selected reconfiguration profile
parameter. An empty profile defaults to the current parameter
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
349

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English