Intel Cyclone 10 GX User Manual

For example, to capture the accumulated errors at any instance of time and read them
back, you can perform the following operations.
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform read-modify-write to address 0x300 and set bit 0 to 1'b1. This action
enables the error and bit counters.
3. To capture the errors accumulated at a particular instant, perform read-modify-
write to address 0x300 and set bit 2 to 1'b1. This takes a snapshot of the error
counters and stores the value to the error count registers.
4. To read the number of errors accumulated when the snapshot was captured,
perform a read from the corresponding error registers 0x301 to 0x307.
5. To reset the bit and error accumulators, perform a read-modify-write to address
0x300 bit 1.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: You can enable the error and bit counters (0x300[0]) and capture the accumulated
bits and errors at different times. The error count registers and bit count registers are
updated with the latest counter values as long as the counter enable bit is set.
Use the PRBS soft accumulators to count the number of accumulated bits and errors
when the hard PRBS blocks are used. PRBS soft accumulators are word-based counter.
The value read out from the PRBS soft accumulators represent the number of words
counted. Hence, in order to obtain the total accumulated bit, user needs to multiply
the value read out from the Accumulated bit pass through count [49:0] registers with
the width of PCS-PMA interface. For Accumulated error count [49:0] registers, it will
count one as long as there are bit errors in a word (be it one bit error in a word or all
the bits in a word are erroneous). Hence, the Accumulated error count [49:0]
registers will not give absolute bit errors counted. For each count, the absolute bit
errors could range from one to the width of PCS-PMA interface.
For more information about using the hard PRBS blocks, refer to the "Using Data
Pattern Generators and Checkers" section.
Table 201. PRBS Accumulator Registers
Address Type Name Description
0x300[0] RW Counter enable (enables both error
and bit counters)
Counter enable (enables both error and bit
counters)
0x300[1] RW Reset Reset the error accumulators
0x300[2] RW Error Count Snapshot Snapshot captures the current value of
accumulated bits and the errors at that time
instance
0x300[3] RO PRBS Done PRBS Done when asserted indicates the verifier
has captured consecutive PRBS patterns and
first pass of polynomial is complete
0x301[7:0] RO Accumulated error count [7:0] Accumulated error count [7:0]
0x302[7:0] RO Accumulated error count [15:8] Accumulated error count [15:8]
0x303[7:0] RO Accumulated error count [23:16] Accumulated error count [23:16]
0x304[7:0] RO Accumulated error count [31:24] Accumulated error count [31:24]
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English