Intel Cyclone 10 GX User Manual

Table 199. Control Registers for the PLL IP Cores
Address Type Register Description
0x2E0[0] RW
pll_powerdown
Drives the PLL powerdown when the Override is set.
0x2E0[1] RW
override_pll_powerd
own
Selects whether the receiver listens to the ADME
pll_powerdown register or the pll_powerdown
port. 1’b1 indicates the receiver will listen to the
ADME pll_powerdown.
Table 200. Status Registers for the PLL IP Cores
Address Type Register Description
0x280[0] RO
pll_locked
Indicates if the PLL is locked. 1'b1 indicates the PLL
is locked.
0x280[1] RO
pll_cal_busy
Indicates the calibration status. 1'b1 indicates the
PLL is currently being calibrated.
0x280[2] RO
avmm_busy
Shows the status of the internal configuration bus
arbitration. 1’b1 indicates PreSICE has control of the
internal configuration bus. 1'b0 indicates the user
has control of the internal configuration bus. Refer to
the Arbitration section for more details.
Related Information
• Calibration on page 373
• Arbitration on page 325
6.15.2.3. PRBS Soft Accumulators
The Pseudo Random Binary Sequence (PRBS) soft accumulators are used in
conjunction with the hard PRBS blocks in the transceiver channel. This section
describes the soft logic that can be added to the Native PHY IP core. To enable this
option, turn on the Enable PRBS Soft Accumulators option in the Native PHY IP
Parameter Editor.
The PRBS soft accumulator has three control bits (Enable, Reset, and Snapshot) and
one status bit (PRBS Done).
• Enable bit—used to turn on the accumulation logic. This bit is also used for
selective error accumulation and to pause the sequence.
• Reset bit—resets the PRBS polynomial and the bit and error accumulators. It also
resets the snapshot registers if independent channel snapshots are used.
• Snapshot bit—captures the current value of the accumulated bits and the errors
simultaneously. This neutralizes the impact of the added read time when the
Avalon-MM interface is used. Capturing a snapshot provides an accurate error
count with respect to the bit count at a specific time.
• PRBS Done bit—indicates the PRBS checker has had sufficient time to lock to the
incoming pattern.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English