Intel Cyclone 10 GX User Manual

Address Type Register Description
0x2E1[0] RW
rx_seriallpbken Enables the rx_seriallopbken feature in the
transceiver. 1’b1 enables reverse serial loopback.
0x2E2[0] RW
rx_analogreset Drives rx_analogreset when the override is set.
0x2E2[1] RW
rx_digitalreset Drives rx_digitalreset when the override is set.
0x2E2[2] RW
tx_analogreset Drives tx_analogreset when the override is set.
0x2E2[3] RW
tx_digitalreset Drives tx_digitalreset when the override is set.
0x2E2[4] RW
override_rx_analogr
eset
Selects whether the receiver listens to the ADME
rx_analogreset register or the rx_analogreset
port. 1'b1 indicates the receiver listens to the ADME
rx_analogreset register.
0x2E2[5] RW
override_rx_digital
reset
Selects whether the receiver listens to the ADME
rx_digitalreset register or the
rx_digitalreset port. 1'b1 indicates the receiver
listens to the ADME rx_digitalreset register.
0x2E2[6] RW
override_tx_analogr
eset
Selects whether the receiver listens to the ADME
tx_analogreset register or the tx_analogreset
port. 1'b1 indicates the receiver listens to the ADME
tx_analogreset register.
0x2E2[7] RW
override_tx_digital
reset
Selects whether the receiver listens to the ADME
tx_digitalreset register or the
tx_digitalreset port. 1'b1 indicates the receiver
listens to the ADME tx_digitalreset register.
Table 198. Status Registers for the Native PHY IP Core
Address Type Register Description
0x280[0] RO
rx_is_lockedtodata
Shows the status of the current channel’s
rx_is_lockedtodata signal. 1’b1 indicates the
receiver is locked to the incoming data.
0x280[1] RO
rx_is_lockedtoref
Shows the status of the current channel’s
rx_is_lockedtoref signal. 1’b1 indicates the
receiver is locked to the reference clock.
0x281[0] RO
tx_cal_busy
Shows the status of the transmitter calibration
status. 1’b1 indicates the transmitter calibration is in
progress.
0x281[1] RO
rx_cal_busy
Shows the status of the receiver calibration status.
1’b1 indicates the receiver calibration is in progress.
0x281[2] RO
avmm_busy
Shows the status of the internal configuration bus
arbitration. 1’b1 indicates PreSICE has control of the
internal configuration bus. 1'b0 indicates the user
has control of the internal configuration bus. Refer to
the Arbitration section for more details. For more
details about calibration registers and performing
user recalibration, refer to the Calibration chapter.
The following control and status registers are available for the PLL IP cores.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English