Intel Cyclone 10 GX User Manual

Address Type Name Description
0x211[7:0] RO Channel Number Shows the unique channel number.
0x212[7:0] RO Duplex Shows the transceiver mode:
• 2'b00 = Unused
• 2'b01 = TX
• 2'b10 = RX
• 2'b11 = Duplex
0x213[0] RO PRBS Soft Enabled Indicates whether the PRBS soft accumulators are
enabled. 1’b1 indicates the accumulators are
enabled.
The following capability registers are available for the PLL IP cores.
Table 196. Capability Registers for the PLL IP Cores
Address Type Name Description
0x200[7:0] RO IP Identifier Unique identifier for the PLL IP instance.
0x204[0] RO Status Register Enabled Indicates if the status registers have been enabled or
not. 1'b1 indicates that the status registers have
been enabled.
0x205[0] RO Control Register Enabled Indicates if the control registers have been enabled
or not. 1'b1 indicates that the control registers have
been enabled.
0x210[7:0] RO Master CGB Enabled Indicates if the Master Clock Generation Block has
been enabled. 1'b1 indicates the master CGB is
enabled.
6.15.2.2. Control and Status Registers
Control and status registers are optional registers that memory-map some of the
status outputs from and control inputs to the Native PHY and PLL.
The following control and status registers are available for the Native PHY IP core.
Table 197. Control Registers for the Native PHY IP Core
Address Type Register Description
0x2E0[0] RW
set_rx_locktodata Asserts the set_rx_locktodata signal to the
receiver. 1'b1 sets the ADME set_rx_locktodata
register. See override_set_rx_locktodata.
0x2E0[1] RW
set_rx_locktoref Asserts the set_rx_locktoref signal to the
receiver. 1'b1 sets the ADME set_rx_locktoref
register. See override_set_rx_locktoref row
below.
0x2E0[2] RW
override_set_rx_loc
ktodata
Selects whether the receiver listens to the ADME
set_rx_locktodata register or the
rx_set_locktodata port. 1'b1 indicates that the
receiver listens to the ADME set_rx_locktodata
register.
0x2E0[3] RW
override_set_rx_loc
ktoref
Selects whether the receiver is listens to the AMDE
set_rx_locktoref register or the
rx_set_locktoref port. 1'b1 indicates that the
receiver listens to the ADME set_rx_locktoref
register.
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English