Intel Cyclone 10 GX User Manual

Parameter Range Description
Enable
tx_enh_fifo_pfull port
On / Off Enables the tx_enh_fifo_pfull port. This signal indicates when
the TX FIFO reaches the specified partially full threshold. This
signal is synchronous to tx_coreclkin.
Enable
tx_enh_fifo_empty
port
On / Off Enables the tx_enh_fifo_empty port. This signal indicates when
the TX FIFO is empty. This signal is synchronous to
tx_coreclkin.
Enable
tx_enh_fifo_pempty
port
On / Off Enables the tx_enh_fifo_pempty port. This signal indicates when
the TX FIFO reaches the specified partially empty threshold. This
signal is synchronous to tx_coreclkin.
Table 14. Enhanced PCS RX FIFO Parameters
Parameter Range Description
RX FIFO Mode Phase-Compensation
Register
Interlaken
10GBASE-R
Basic
Specifies one of the following modes for Enhanced PCS RX FIFO:
• Phase Compensation: This mode compensates for the clock
phase difference between the read clocks rx_coreclkin or
tx_clkout and the write clock rx_clkout.
•
Register : The RX FIFO is bypassed. The
rx_parallel_data, rx_control, and
rx_enh_data_valid are registered at the FIFO output. The
FIFO's read clock rx_coreclkin and write clock rx_clkout
are tied together.
• Interlaken: Select this mode for the Interlaken protocol. To
implement the deskew process, you must implement an FSM
that controls the FIFO operation based on FIFO flags. In this
mode the FIFO acts as an elastic buffer.
• 10GBASE-R: In this mode, data passes through the FIFO
after block lock is achieved. OS (Ordered Sets) are deleted and
Idles are inserted to compensate for the clock difference
between the RX PMA clock and the fabric clock of +/- 100 ppm
for a maximum packet length of 64000 bytes.
• Basic: In this mode, the RX FIFO acts as an elastic buffer. This
mode allows driving write and read side of FIFO with different
clock frequencies. tx_coreclkin or rx_coreclkin must
have a minimum frequency of the lane data rate divided by
66. The frequency range for tx_coreclkin or
rx_coreclkin is (data rate/32) - (data rate/66). The
gearbox data valid flag controls the FIFO read enable. You can
monitor the rx_enh_fifo_pfull and rx_enh_fifo_empty
flags to determine whether or not to read from the FIFO. For
additional details refer to Enhanced PCS FIFO Operation on
page 164.
Note:
The flags are for Interlaken and Basic modes only. They
should be ignored in all other cases.
RX FIFO partially full
threshold
18-29 Specifies the partially full threshold for the Enhanced PCS RX
FIFO. The default value is 23.
RX FIFO partially
empty threshold
2-10 Specifies the partially empty threshold for the Enhanced PCS RX
FIFO. The default value is 2.
Enable RX FIFO
alignment word
deletion (Interlaken)
On / Off When you turn on this option, all alignment words (sync words),
including the first sync word, are removed after frame
synchronization is achieved. If you enable this option, you must
also enable control word deletion.
Enable RX FIFO control
word deletion
(Interlaken)
On / Off When you turn on this option, Interlaken control word removal is
enabled. When the Enhanced PCS RX FIFO is configured in
Interlaken mode, enabling this option, removes all control words
after frame synchronization is achieved. Enabling this option
requires that you also enable alignment word deletion.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English