The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It
stays high until you reset it with rx_prbs_err_clr.
•
rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr—Used to reset the rx_prbs_err signal.
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
Use the PRBS soft accumulators to count the number of accumulated bits and errors
when the hard PRBS blocks are used. For more information about using the
accumulators and reading the error values, refer to the PRBS Soft Accumulators
section.
Table 203. Register Map for PRBS Generators for bonded and non bonded designs
Description Reconfiguration
Address
Reconfiguration
Bits
Value Attribute Encoding Attribute Name
Select PRBS
generator block
0x006 [2:0] 3'b100 prbs_pat tx_pma_data_sel
0x008 [6:5] 2'b00
Enable PRBS 9 in
10-bit mode
0x006 [3] 1'b1 prbs9_10b prbs9_dwidth
Enable PRBS 9 in
64-bit mode
1'b0 prbs9_64b
Enable PRBS
generator clock
0x006 [6] 1'b1 prbs_clk_en prbs_clken
Disable PRBS
generator clock
1'b0 prbs_clk_dis
Enable PRBS 7
pattern
0x007 [7:4] 4'b0001 prbs_7 prbs_gen_pat
0x008 [4] 1'b0
Enable PRBS 9
pattern
0x007 [7:4] 4'b0010 prbs_9
0x008 [4] 1'b0
Enable PRBS 15
pattern
0x007 [7:4] 4'b0100 prbs_15
0x008 [4] 1'b0
Enable PRBS 23
pattern
0x007 [7:4] 4'b1000 prbs_23
0x008 [4] 1'b0
enable PRBS 31
pattern
0x007 [7:4] 4'b0000 prbs_31
0x008 [4] 1'b1
Serializer 64-bit
width mode
0x110 [2:0] 3'b011 sixty_four_bit ser_mode
Serializer 10-bit
width mode
3'b100 ten_bit
Enable xN non
bonding
0x111 [4:0] 5'b11000 xN_non_bonding
(31)
x1_clock_source_sel
0x119 [0] 1'b0
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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