Intel Cyclone 10 GX User Manual

Parameter Range Description
Enable
tx_std_pcfifo_empty
port
On / Off
Enables the tx_std_pcfifo_empty port. This signal indicates
when the standard TX phase compensation FIFO is empty. This
signal is synchronous with tx_coreclkin.
Enable
rx_std_pcfifo_full port
On / Off
Enables the rx_std_pcfifo_full port. This signal indicates
when the standard RX phase compensation FIFO is full. This signal
is synchronous with rx_coreclkin.
Enable
rx_std_pcfifo_empty
port
On / Off
Enables the rx_std_pcfifo_empty port. This signal indicates
when the standard RX phase compensation FIFO is empty. This
signal is synchronous with rx_coreclkin.
Table 26. Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte
serializer
Disabled
Serialize x2
Serialize x4
Specifies the TX byte serializer mode for the Standard PCS. The
transceiver architecture allows the Standard PCS to operate at
double or quadruple the data width of the PMA serializer. The byte
serializer allows the PCS to run at a lower internal clock frequency
to accommodate a wider range of FPGA interface widths.
Serialize x4 is only applicable for PCIe protocol implementation.
Enable RX byte
deserializer
Disabled
Deserialize x2
Deserialize x4
Specifies the mode for the RX byte deserializer in the Standard
PCS. The transceiver architecture allows the Standard PCS to
operate at double or quadruple the data width of the PMA
deserializer. The byte deserializer allows the PCS to run at a lower
internal clock frequency to accommodate a wider range of FPGA
interface widths. Deserialize x4 is only applicable for PCIe
protocol implementation.
Table 27. 8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/10B
encoder
On / Off When you turn on this option, the Standard PCS enables the TX
8B/10B encoder.
Enable TX 8B/10B
disparity control
On / Off When you turn on this option, the Standard PCS includes disparity
control for the 8B/10B encoder. You can force the disparity of the
8B/10B encoder using the tx_forcedisp control signal.
Enable RX 8B/10B
decoder
On / Off When you turn on this option, the Standard PCS includes the
8B/10B decoder.
Table 28. Rate Match FIFO Parameters
Parameter Range Description
RX rate match FIFO mode Disabled
Basic 10-bit PMA
width
Basic 20-bit PMA
width
GbE
PIPE
PIPE 0 ppm
Specifies the operation of the RX rate match FIFO in the Standard
PCS.
Rate Match FIFO in Basic (Single Width) Mode on page 173
Rate Match FIFO Basic (Double Width) Mode on page 175
Rate Match FIFO for GbE on page 92
Transceiver Channel Datapath for PIPE on page 123
RX rate match insert/
delete -ve pattern (hex)
User-specified 20 bit
pattern
Specifies the -ve (negative) disparity value for the RX rate match
FIFO as a hexadecimal string.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English