Intel Cyclone 10 GX User Manual

Name Direction Clock Domain Description
tx_pma_iqtxrx_clko
ut
Output Clock This port is available if you turn on Enable tx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be used to
cascade the TX PMA output clock to the input of a PLL.
tx_pma_elecidle[<n
>-1:0]
Input Asynchronous When you assert this signal, the transmitter is forced to
electrical idle. This port has no effect when you configure the
transceiver for the PCI Express protocol.
rx_seriallpbken[<n
>-1:0]
Input Asynchronous This port is available if you turn on Enable rx_seriallpbken
port in the Transceiver Native PHY IP core Parameter
Editor. The assertion of this signal enables the TX to RX
serial loopback path within the transceiver. This signal can be
enabled in Duplex or Simplex mode. If enabled in Simplex
mode, you must drive the signal on both the TX and RX
instances from the same source. Otherwise the design fails
compilation.
Table 40. RX PMA Ports
Name Direction Clock Domain Description
rx_serial_data[<n>
-1:0]
Input N/A Specifies serial data input to the RX PMA.
rx_cdr_refclk0
Input Clock Specifies reference clock input to the RX clock data recovery
(CDR) circuitry.
Optional Ports
rx_cdr_refclk1–
rx_cdr_refclk4
Input Clock Specifies reference clock inputs to the RX clock data recovery
(CDR) circuitry.
rx_analog_reset_ac
k
Output Asynchronous Enables the optional rx_pma_analog_reset_ack output. This
port should not be used for register mode data transfers.
rx_pma_clkout
Output Clock This clock is the recovered parallel clock from the RX CDR
circuitry.
rx_pma_div_clkout
Output Clock The deserializer generates this clock. This is used to drive core
logic, PCS-to-FPGA fabric interface, or both. If you specify a
rx_pma_div_clkout division factor of 1 or 2, this clock output
is derived from the PMA parallel clock (low speed parallel
clock). If you specify a rx_pma_div_clkout division factor of
33, 40, or 66, this clock is derived from the PMA serial clock.
This clock is commonly used when the interface to the RX FIFO
runs at a different rate than the PMA parallel clock (low speed
parallel clock) frequency, such as 66:40 applications.
rx_pma_iqtxrx_clko
ut
Output Clock This port is available if you turn on Enable rx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be used to
cascade the RX PMA output clock to the input of a PLL.
rx_pma_clkslip
Output Clock When asserted, indicates that the deserializer has either
skipped one serial bit or paused the serial clock for one cycle to
achieve word alignment. As a result, the period of the parallel
clock could be extended by 1 unit interval (UI) during the clock
slip operation.
rx_is_lockedtodat
a[<n>-1:0]
Output
rx_clkout
When asserted, indicates that the CDR PLL is locked to the
incoming data, rx_serial_data.
rx_is_lockedtoref[
<n>-1:0]
Output
rx_clkout
When asserted, indicates that the CDR PLL is locked to the
input reference clock.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
51

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English