Intel Cyclone 10 GX User Manual

Name Direction Clock Domain Description
rx_set_locktodata[
<n>-1:0]
Input Asynchronous This port provides manual control of the RX CDR circuitry.
rx_set_locktoref[<
n>-1:0]
Input Asynchronous This port provides manual control of the RX CDR circuitry.
rx_seriallpbken[<n
>-1:0]
Input Asynchronous This port is available if you turn on Enable rx_ seriallpbken
port in the Transceiver Native PHY IP core Parameter Editor.
The assertion of this signal enables the TX to RX serial
loopback path within the transceiver. This signal is enabled in
Duplex or Simplex mode. If enabled in Simplex mode, you
must drive the signal on both the TX and RX instances from
the same source. Otherwise the design fails compilation.
rx_prbs_done[<n>-1
:0]
Output
rx_coreclkin
or rx_clkout
When asserted, indicates the verifier has aligned and captured
consecutive PRBS patterns and the first pass through a
polynomial is complete.
rx_prbs_err[<n>-1:
0]
Output
rx_coreclkin
or rx_clkout
When asserted, indicates an error only after the
rx_prbs_done signal has been asserted. This signal gets
asserted for three parallel clock cycles for every error that
occurs. Errors can only occur once per word.
rx_prbs_err_clr[<n
>-1:0]
Input
rx_coreclkin
or rx_clkout
When asserted, clears the PRBS pattern and deasserts the
rx_prbs_done signal.
Table 41. Calibration Status Ports
Name Direction Clock Domain Description
tx_cal_busy[<n>-1:0]
Output Asynchronous When asserted, indicates that the initial TX
calibration is in progress. For both initial and
manual recalibration, this signal will be asserted
during calibration and will deassert after
calibration is completed. You must hold the
channel in reset until calibration completes.
rx_cal_busy[<n>-1:0]
Output Asynchronous When asserted, indicates that the initial RX
calibration is in progress. For both initial and
manual recalibration, this signal will be asserted
during calibration and will deassert after
calibration is completed.
Table 42. Reset Ports
Name Direction Clock Domain
(20)
Description
tx_analogreset[<n>-1:
0]
Input Asynchronous Resets the analog TX portion of the transceiver
PHY.
tx_digitalreset[<n>-1
:0]
Input Asynchronous Resets the digital TX portion of the transceiver
PHY.
rx_analogreset[<n>-1:
0]
Input Asynchronous Resets the analog RX portion of the transceiver
PHY.
rx_digitalreset[<n>-1
:0]
Input Asynchronous Resets the digital RX portion of the transceiver
PHY.
(20)
Although the reset ports are not synchronous to any clock domain, Intel recommends that you
synchronize the reset ports with the system clock.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English