Intel Cyclone 10 GX User Manual

Table 50. Gearbox
Name Direction Clock Domain Description
rx_bitslip[<n>-1:0]
Input
rx_clkout The rx_parallel_data slips 1 bit for every positive edge
of the rx_bitslip input. Keep the minimum interval
between rx_bitslip pulses to at least 20 cycles. The
maximum shift is < pcswidth -1> bits, so that if the PCS is
64 bits wide, you can shift 0-63 bits.
tx_enh_bitslip[<n>-1:0
]
Input
rx_clkout
The value of this signal controls the number of bits to slip
the tx_parallel_data before passing to the PMA.
2.4.9.1. Enhanced PCS TX and RX Control Ports
This section describes the tx_control and rx_control bit encodings for different
protocol configurations.
When Enable simplified data interface is ON, all of the unused ports shown in the
tables below, appear as a separate port. For example: It appears as
unused_tx_control/ unused_rx_control port.
Enhanced PCS TX Control Port Bit Encodings
Table 51. Bit Encodings for Interlaken
Name Bit Functionality Description
tx_control
[1:0] Synchronous header The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[2] Inversion control A logic low indicates that the built-in disparity
generator block in the Enhanced PCS maintains
the Interlaken running disparity.
[7:3] Unused
[8] Insert synchronous header error or
CRC32
You can use this bit to insert synchronous header
error or CRC32 errors. The functionality is similar
to tx_err_ins. Refer to tx_err_ins signal
description for more details.
[17:9] Unused
Table 52. Bit Encodings for 10GBASE-R
Name Bit Functionality
tx_control
[0]
XGMII control signal for parallel_data[7:0]
[1]
XGMII control signal for parallel_data[15:8]
[2]
XGMII control signal for parallel_data[23:16]
[3]
XGMII control signal for parallel_data[31:24]
[4]
XGMII control signal for parallel_data[39:32]
[5]
XGMII control signal for parallel_data[47:40]
[6]
XGMII control signal for parallel_data[55:48]
[7]
XGMII control signal for parallel_data[63:56]
[17:8] Unused
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
59

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English