Intel Cyclone 10 GX User Manual

Name Direction Clock Domain Description
frame generator block. This bus must be held constant for 5
clock cycles before and after the tx_enh_frame pulse. The
following encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
tx_enh_frame_burst_en[
<n>-1:0]
Input
tx_clkout
If Enable frame burst is enabled, this port controls frame
generator data reads from the TX FIFO to the frame
generator. It is latched once at the beginning of each
Metaframe. If the value of tx_enh_frame_burst_en is 0,
the frame generator does not read data from the TX FIFO
for current Metaframe. Instead, the frame generator inserts
SKIP words as the payload of Metaframe. When
tx_enh_frame_burst_en is 1, the frame generator reads
data from the TX FIFO for the current Metaframe. This port
must be held constant for 5 clock cycles before and after
the tx_enh_frame pulse.
rx_enh_frame[<n>-1:0]
Output
rx_clkout
When asserted, indicates the beginning of a new received
Metaframe. This signal is pulse stretched.
rx_enh_frame_lock[<n>-
1:0]
Output
rx_clkout
When asserted, indicates the Frame Synchronizer state
machine has achieved Metaframe delineation. This signal is
pulse stretched.
rx_enh_frame_diag_stat
us[2 <n>-1:0]
Output
rx_clkout
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This signal is latched
when a valid diagnostic word is received in the end of the
Metaframe while the frame is locked. The following
encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
rx_enh_crc32_err[<n>-1
:0]
Output
rx_clkout
When asserted, indicates a CRC error in the current
Metaframe. Asserted at the end of current Metaframe. This
signal gets asserted for 2 or 3 cycles.
Table 48. 10GBASE-R BER Checker
Name Direction Clock Domain Description
rx_enh_highber[<n>-1:0
]
Output
rx_clkout
When asserted, indicates a bit error rate that is greater
than 10
-4
. For the 10GBASE-R protocol, this BER rate
occurs when there are at least 16 errors within 125 µs.
This signal gets asserted for 2 to 3 clock cycles.
rx_enh_highber_clr_cn
t[<n>-1:0]
Input
rx_clkout
When asserted, clears the internal counter that indicates
the number of times the BER state machine has entered
the BER_BAD_SH state.
rx_enh_clr_errblk_coun
t[<n>-1:0] (10GBASE-R)
Input
rx_clkout
When asserted the error block counter resets to 0.
Assertion of this signal clears the internal counter that
counts the number of times the RX state machine has
entered the RX_E state.
Table 49. Block Synchronizer
Name Direction Clock Domain Description
rx_enh_blk_lock<n>-1:0
]
Output
rx_clkout
When asserted, indicates that block synchronizer has
achieved block delineation. This signal is used for
10GBASE-R and Interlaken.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English