Intel Cyclone 10 GX User Manual

Figure 21. 10X12.5 Gbps xN Bonding
Transceiver PLL
Instance (6.25 GHz)
ATX PLL
Native PHY Instance
(10 Ch Bonded 12.5 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Transceiver Bank 2
TX Channel
TX Channel
TX Channel
Master
CGB
xN
Transceiver Bank 1
Note: Intel Cyclone 10 GX devices have transceiver channels that can support data rates
up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps
for backplane communication.
TX Channel
TX Channel
Related Information
• Implementing x6/xN Bonding Mode on page 236
For detailed information on xN bonding limitations
• Using PLLs and Clock Networks on page 231
For more information about implementing PLLs and clocks
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State
Machine
The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken
elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port
signals are provided to the FPGA fabric. Connect these signals to the MAC layer as
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English